@W: MO129 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":35:0:35:5|Sequential instance compute_u.state[4] is reduced to a combinational gate by constant propagation.
@W: BN132 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":35:0:35:5|Removing instance compute_u.cal_number[3] because it is equivalent to instance compute_u.cal_number[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":35:0:35:5|Removing instance compute_u.cal_number[2] because it is equivalent to instance compute_u.cal_number[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"c:\users\test\desktop\calculator_fpga_mico8\source\compute.v":229:0:229:5|Register bit uart_data_1[6] (in view view:work.compute(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MT420 |Found inferred clock calculator|clk_in with period 1000.00ns. Please declare a user-defined clock on object "p:clk_in"
